1. Field of the Invention
The present invention relates to static random access memories (SRAMs) and, more particularly, to SRAMs which have improved stability.
2. Description of the Related Art
Reduced geometry integrated circuit designs are adopted to increase the density of devices within integrated circuits, thereby increasing performance and decreasing the real costs for the integrated circuits. Modern integrated circuit memories, including DRAMs, SRAMs, ROMs, EEPROMS, etc., are prominent examples of the application of this strategy. The density of memory cells within integrated circuit memories continues to increase, accompanied by a corresponding drop in the cost per bit of storage within such devices. Increases in density are accomplished by forming smaller structures within devices and by reducing the separation between devices or between the structures that make up the devices. Often, these smaller design rules are accompanied by layout, design and architectural modifications which are either made possible by the reduced device sizes or are necessary to maintain performance when such smaller design rules are implemented. As an example, the reduced operating voltages used in many conventional integrated circuits are made possible by improvements in design, such as reduced gate oxide thicknesses and improved tolerance controls in lithographic processing. On the other hand, reduced design rules make reduced operating voltages essential to limit the effects of hot carriers generated in small size devices operating at higher, previously conventional operating voltages.
Making static random access memories (SRAMs) in accordance with smaller design rules, as well as using reduced internal operating voltages, can reduce the stability of SRAM cells. Reduced operating voltages and other design changes can reduce the voltage margins which ensure that an SRAM cell remains in a stable data state during a data read operation, increasing the likelihood that the read operation could render indeterminate or lose entirely the data stored in the SRAM cell. Typical SRAM designs include two or four MOS transistors coupled together in a latch configuration having two charge storage nodes for storing the charge states which correspond to the data. Data are read out of the conventional SRAM cell in a non-destructive manner by selectively coupling each charge storage node to a corresponding one of a pair of complementary bit lines. The selective coupling is accomplished by a pair of pass transistors, each pass transistor connected between one of the charge storage nodes and the corresponding one of the complementary bit lines. Word line signals are provided to the gates of the pass transistors to switch the pass transistors ON during data read operations. Charge flows through the ON pass transistors to or from the charge storage nodes, discharging one of the bit lines and charging the other of the bit lines. The voltage changes on the bit lines are sensed by a differential amplifier.
For the SRAM cell's latch to remain stable during such a data reading operation, at least one of the charge storage nodes within the SRAM must charge or discharge at a faster rate than charge flows from or to the corresponding bit line. In the past, this control has been maintained by making the channel of the pass transistor connected to the particular charge storage node narrower and/or longer than the channel of at least one of the SRAM cell transistors having a drain connected to the particular charge storage node. This geometry allows more current to flow through the at least one SRAM cell transistor than through the corresponding pass transistor, consequently, the charge storage node charges or discharges faster than the corresponding bit line discharges or charges.
This geometry has certain disadvantages and limitations, however. For example, making the channel of the pass transistor narrow and long makes data read and write operations slow. In addition, the relative geometries of the different cell and pass transistors place limitations on exactly how small a particular SRAM cell can be made.